1. Field of the Invention
The present invention relates generally to a semiconductor package structure.
2. Description of Related Art
In addition to conventional wire bonding packages, the semiconductor industry developed, thanks to ever-evolving semiconductor packaging technology, various semiconductor device packages. For example, an IC semiconductor chip is directly embedded in a package substrate and electrically integrated therewith so as to reduce the whole size of the semiconductor device and enhance the electrical function thereof. Such a package type has become a mainstream.
FIGS. 1A to 1D shows a method for fabricating a conventional package structure, wherein FIG. 1A′ is a top view of FIG 1A.
Referring to FIGS. 1A and 1A′, a first carrier board 11 having a first surface 11a and an opposing second surface 11b is provided, and a rectangular through hole 110 penetrating the first surface 11a and the second surface 11b is formed in the first carrier board 11. As shown in the drawings, a second carrier board 12 is provided and coupled to the second surface 11b of the first carrier board 11.
Referring to FIG. 1B, a semiconductor chip 13 is provided, which has an active surface 13a with a plurality of electrode pads 131 thereon and an inactive surface 13b opposing the active surface 13a. As shown in the drawing, the inactive surface 13b of the semiconductor chip 13 is fixed in position to the second carrier board 12 in the through hole 110 of the first carrier board 11 through an adhesion layer 14.
Referring to FIG. 1C, a dielectric layer 15 is formed on the first carrier board 11 and the active surface 13a of the semiconductor chip 13 by laminating. As shown in the drawing, the dielectric layer 15 fills the gap between the through hole 110 and the semiconductor chip 13.
As shown in FIG. 1D, a wiring layer 16 is formed on the dielectric layer 15, and a plurality of conductive vias 161 are formed in the dielectric layer 15 for electrical connection with the electrode pads 131 of the semiconductor chip 13.
However, in the above-described prior art, since a gap exists between the semiconductor chip 13 and the through hole 110, the semiconductor chip 13 received in the through hole 110 may have a positional offset e caused by pressure or air bubbles created during the laminating of the dielectric layer 15, and in consequence the positional offset e contributes to an alignment offset between the conductive vias 161 and the electrode pads 131 and even causes failure of the electrical connection therebetween.
Therefore, it is imperative to overcome the above-described drawbacks of the prior art.